AddressJOB AD:
ROLE: ASIC/FPGA Development Engineer
LOCATION: UK-London
SALARY: Highly Competitive
DURATION: Permanent
Join a London based company who have developed an innovative approach to image and video compression that is driving major change in the encoding sector.
They are seeking experienced individuals to join its compression development team for high-speed development of 8K/4k and HD video processing on ASIC and prototyped on the FPGA platform.
The company places high importance on a positive environment where talented individuals deliver exceptional products.The candidate must share that vision and be passionate about "right first time" execution, as well as being a strong communicator and team player who strives to succeed.
Responsibilities:
Take the conceptual, high level mathematical work of their research group and architect RTL for ASIC implementation reusable for FPGA prototyping.
Understand and maintain the clients existing IP ASIC codec catalogue Create test benches to verify RTL functionality using test vectors or random stimulus methodology Create clear, concise and verifiable technical specifications Synthesize design using synthesis and P&R tools, verifying against predetermined requirements.
Support the development of in-house python, octave or C++ models for RTL verification Maintain and support current ASIC/FPGA deployments with customers and third parties
Qualifications, Experience and Competencies Requirements:
At least four years' experience of ASIC and FPGA development in Verilog or VHDL including synthesis and static timing analysis for FMAX optimisation Strong knowledge and experience of digital design principles and concepts for area and throughput optimization.
Strong understanding of AMD/Xilinx workflow (Vivado, HLS) Good understanding of the Intel/Altera workflow (Quartus, Qsys and tcl) Preferably experience of integrating 3rd party IP blocks (e.g. soft processors, SDI, PCie, DDR and network cores) Preferably experience of design simulation in Riviera-Pro, Questa and scripting workflow Willingness to independently and rapidly learn new subjects at the level of depth and rigor that is needed to progress development activities An understanding of python, octave and C++ to support verification activities Experience of development methodologies such as Agile and willingness to prioritise development activities in accordance with commercial priorities A background in Broadcast video processing/encoding and signal processing would be advantageous but not essential
