Senior Physical Design Engineer

Up to 80,000

Farnborough
Your new company

This exciting, multi-award winning global communications company is looking to expand its UK team to manufacture and support satellite tracking and IoT products and services. Established over ten years ago by leading voices in the satellite industry, they are seeking a knowledgeable and creative person with vision to join a team that develops truly global products.

Their products radically increase system performance and reduce the weight and power requirements of terminals, payloads and gateway equipment. With satellite communication expertise and full development capabilities, the company delivers the industry's smallest VSATs and multi-beam electronically steered antenna arrays for a variety of mobile applications and services, such as Connected Car, IoT, consumer broadband, airline broadband communications, communication payloads and more.
We are looking for the best of the best, so if you are looking for a challenging new role in a dynamic company, read on!

Your new role

Be part of a dynamic and motivated multinational Physical Design team, taking part in developing a state-of-the-art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation of radiation-hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.

• Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc)
• Full block level timing closure and manufacturing checks signoff including power planning and analysis
• Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level
• Insertion of DFT test structures and chip level integration, capture, and simulation

Skills needed to succeed

• COT/ASIC Physical Design flow covering: Synthesis, Floor planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/pattern generation.
• Deep sub-micron (28nm or below) process technologies
• Industry standard design processes for deep sub-micron designs
• Problem-solving and analytical skills
• Practical use of scripting languages Tcl/Python/Perl etc
• Experience of at least one of the following EDA tool flows: Cadence or Synopsys
• Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow
• Managing/Interfacing to sub-contract design service providers

What you need to do now
If you're interested in this role, click 'apply now' to forward an up-to-date copy of your CV, or call us now.
If this job isn't quite right for you, but you are looking for a new position, please contact us for a confidential discussion on your career.

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