Senior Verification Engineer

This position provides an exceptional opportunity for a highly motivated and experienced Verification Engineer to join the engaging, hardworking, and creative System IP team.

The latest and most advanced hardware design and verification methodologies are employed to create the System IPs that will drive the development of the next generation of compute solutions for every area of technology, from mobile phones, to servers, to autonomous vehicles.

The Arm Central Engineering – System IP group in Cambridge, is responsible for specifying, developing and validating IP products from the Arm CoreLink and CoreSight IP portfolio responsible for interrupt control, inter-process communication, trace and debug solutions. These IPs are an essential part of systems that scale from real-time embedded to hyperscale cloud. We are looking for verification specialists to join our team and play an integral role in developing technology that makes people's lives better!

Responsibilities:

For this role we are looking for engineers who are capable of leading the verification of a unit within a project through all phases of the design and verification flow. This includes:

• Working closely with the RTL design team to develop comprehensive verification strategies
• Creating and reviewing design verification documentation
• Designing and implementing SystemVerilog/UVM based verification IP and testbenches
• Improving existing testbenches to increase performance, quality and efficiency
• Testing and debugging Verilog RTL
• Defining and implementing functional coverage as well as enhancing the testbench to ensure coverage closure
• Planning and tracking tasks to meet the targets at the planned time
• Driving the execution to ensure the quality of the design work done along with on time delivery
• Coaching and mentoring junior engineers

Required Skills and Experience:

• Substantial experience of RTL verification for complex IP products
• Proficiency in a hardware verification language, preferably System Verilog / UVM
• Experience of development of coverage-driven constrained random test environments
• Experience producing specifications and documentation describing complex designs
• Strong communication skills and ability to work well as part of a team

'Nice to Have' Skills and Experience:

• Experience of low power RTL design and verification
• Proficiency in scripting languages such as Python or Perl
• Strong software engineering skills including understanding of object-oriented programming, data structures, and algorithms
• Knowledge of formal verification techniques and tools
• Competency in C/C++ or Assembly language (preferably Arm) programming
• Competency in a hardware design language, preferably Verilog
• Practical experience of working on microprocessor or complex system interconnect and peripheral designs
• Understanding of the fundamentals of computer architecture
• Exposure to all stages of the design cycle: initial concept, specification, implementation and testing, documentation and support
• Some team leadership experience, including planning and managing tasks
• Line management experience

In Return

There will be the opportunity to utilise your engineering skills to develop cutting-edge technology, directly influencing the efficiency and performance of systems deployed in millions of devices. You can share your ideas with a wide group of world-leading engineers developing your technical leadership and influencing skills and build towards becoming a key part of the team.

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