Staff SoC Performance Modelling Engineer

Job Overview:

The Central Technology (CT) Group at Arm is responsible for examining and defining the future of Arm solutions to the next generation of challenges.

We consider the solutions at a full system level involving many components developed by several teams. To get the best out of Arm’s IP, we use performance models to explore system architecture and configuration and ensure that the compute subsystems created using Arm IP deliver the best performance power and area (PPA) for markets like premium mobile, infrastructure and automotive.

As a Performance Modelling Engineer, you will be responsible for creating these system level performance models, exploring new technologies and evaluating them. To do so, you will need to understand new features, implement them using performance models, evaluate their behaviour and work with system architects to improve their performance.

Responsibilities:

• Engaging with architects on future systems within Arm.
• Creating full system models using a range of IP models from across the company.
• Running system performance characterization and optimization studies.
• Developing exploration models for system components like Coherent/Non-Coherent interconnects, Last Level Caches (LLC/SLC), Dynamic memory controller (DDR5, LPDDR5/6, HBM etc).
• Leading exploration studies aimed at determining the efficiency of proposed IP features in a system context.
• Building infrastructure to enable better inspection and root-cause analysis of such systems.
• Helping to define future direction of system Performance Modelling across Arm.

Required Skills and Experience:

• Bachelors, Masters, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science with a strong computer architecture, microarchitecture, performance experience.
• Experience in developing and using cycle approximate/accurate performance models.
• Experience in generating pre-silicon/pre-RTL performance projections and performance bottleneck debug and analysis.
• Strong C/C++ programming and debugging skills.
• Excellent interpersonal and communication skills.
• Ability to work in teams and to collaborate with colleagues in other groups and sites.
• Proactive and motivated.

“Nice To Have” Skills and Experience:

• Knowledge of on-chip bus protocols such as AMBA, coherency flows, interconnects, memory subsystems
• Knowledge of CPU microarchitecture.
• Experience in evaluating/benchmarking system level performance using performance monitors.
• Exposure to performance analysis and tuning in pre- and post-silicon environments.

In Return:

We offer a competitive reward package including annual bonus, RSUs, healthcare and wellness support. As well as other benefits such as a supplementary pension, and 25 days annual leave (with option to buy an additional 5 days per year). There's even an on-site gym and social events organised within the company!