Senior Verification Engineer

Key Responsibilities:

• Minimum 7 years of experience as Digital IP Level Verification Engineer with System Verilog UVM

(SoC/Subsystem is experience is NOT preferred).

• Must be available for at least 1 year, preferably longer – Will have to be located inside UK.

• A self-starter and a quick learner.

• Excellent communication skills.

• Work as part of a team and implement test bench using System Verilog UVM.

• Efficiently debug SV model or c-model or RTL.

• Analyzing test regression fails, debugging and fixing.

• Develop Efficient Coverage model and effectively close coverage targets. Nice to have tool specific experiences in :

Xcellium

VManager

Clearcase

Key Skills:

• Bachelors in Electronics Engineering is a minimum requirement

• Masters in Electronics or Computer Science Engineering is an added advantage

• 7+ years of Industry experience in the industry

• Exposure to working in multi-national environment is required

• An attitude to learn and grow. Adaptability and flexibility is desired