SMTS Logic Designer

Client Information:

• Premier Chip and Silicon IP provider. As a Designer, Integrator & Tester, you will be reporting to the PCIe IP Design Manager.
• You will develop features and reference designs to show the potential of the IP, simulate the IP and to prototype the IP on cutting edge FPGAs.
• You have 2 days a week available to work from home, spending 3 days a week in the office.

Responsibilities:

• Develop IP features
• Define reference design / example architectures to best demonstrate features of PCIe / CXL controller IP
• Develop these designs using Verilog
• Perform simulation with various simulators
• Perform FPGA synthesis implementation flow
• Perform HW Test and debug on cutting edge platforms
• Scripting for continuous integration & automation

Requirements:

• RTL coding : Verilog / VHDL
• Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
• Minimum 4+ years of experience with RTL Design