Senior Digital Design Engineer

Job Description:

• As a Senior Digital Design Engineer you will be working to implement high performance AI inference solutions on FPGA. You will contribute to IP library in SystemVerilog and build out complete FPGA design solutions for customers. You will work as part of a diverse team of developers and researchers, on IP that is core to inference products.
• You will use your experience to deliver highly performant, well tested and extensible code for some of the most widely deployed AI in modern data centres. You'll work closely with software and machine learning engineers, integrating against my clients compiler/runtime/driver stack, to build high-reliability, low-latency, and high-throughput inference applications.
• You will work with the latest AI capable FPGAs from multiple FPGA vendors to develop RTL in SystemVerilog. You will generate maintainable and parameterizable IP components, to enable reuse across multiple FPGAs and applications.
• You will package IP into full solution implementations, achieve timing closure through floor planning and test solutions on the board. You will make low level software interface code changes to support integration with the clients software stacks. You will work in a Linux development environment.
• You will help to define the ways of working in the FPGA team, including coding standards and test. You will help the team to plan activities using Agile scrum methodology.

Responsibilities:

• - Writing and testing IP components in SystemVerilog for FPGA
• - Building full applications for FPGA using our IP library
• - Integrating with third party IP for external memory PCIe subsystems
• - Extending IP verification code and integrating into automated test environments
• - Working with software interface routines to support FPGA integration into the software stacks
• - Learning about a range of Machine Learning inference optimization techniques
• - Providing technical support for customer engagements

Recommended Experience and Skills:

• - At least 5 years experience generating clear, well-documented, and well-tested SystemVerilog, Verilog or VHDL code
• - Masters degree in Engineering, Mathematics or other Scientific Discipline
• - Worked with FPGA EDA tools such as Quartus or Vivado
• - Worked with software languages such as C, C++, Python
• - Familiarity with Linux development environments, version control and CI systems
• - Experience of bringing up full FPGA designs and debugging on hardware
• - Experience optimising RTL designs to achieve timing closure
• - Good verbal and written communication skills
• - [Nice to have] - Familiarity with neural network architectures
• - [Nice to have] - Interest in Functional Programming Languages