Principal Design Engineer

ARM’s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate.

This position is an excellent opportunity for an experienced and highly motivated Design Engineer to join the hardworking System IP team!

This is a fast-paced technical role employing the latest hardware design methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems!

The Interconnect team develops the Arm Corelink Interconnect IP family. Our Interconnects and NoCs are designed for intelligent connected systems across a wide range of applications including mobile, IoT, networking infrastructure, automotive etc. The highly scalable IP is optimised for AMBA-compliant SoC connectivity and can be customised for multiple performance points

• Analyse proposed specifications to understand implementation challenges and opportunities, working with the architects to improve and refine the ideas
• Plan, track and coordinate tasks for yourself and your team
• Work with modelling, verification, performance analysis and back-end implementation colleagues to ensure your design meets all the functional and performance requirements
• Improve design methodology to meet evolving needs

You will be responsible for development of one or more functional blocks of the IP. Possess an in-depth understanding of all the aspects of the products’ successful delivery, including low-power design techniques, awareness of the impact of design decisions on system performance, ability to produce designs that are area efficient, and the verification techniques that are employed to ensure high-quality, innovative designs

• Demonstration of a strong delivery record of high quality, low power, high performance sophisticated micro-architecture and RTL design using System Verilog, Verilog or VHDL in reasonable timescales.
• Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices.
• Knowledgeable on ASIC (or FPGA) design methodology, IP signoff methods with a deep understanding on timing/area/complexity trade-offs for complex data path designs.

• Team leadership and mentoring experience
• Knowledge of memory system interconnect protocols (e.g. AMBA ACE-Lite or AXI)
• Solid understanding of SystemVerilog Assertions (SVA) and formal verification
• Experience of a scripting language such as Perl, Tcl, C shell, Pytho
• Knowledge of a number hardware verification languages e.g. SystemVerilog
• You have already worked on Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508)

In return -

You will get to utilise your engineering skills to build support for the technologies and influence millions of devices for years to come!

#LI-JC1